Output buffer circuits are commonly implemented in semiconductor integrated circuits including, for example, memory circuits and logic circuits, as a means of transferring and amplifying signals provided to an input buffer circuit of another device. Chips as used herein refer to semiconductor integrated circuits. Chips may share an external I/O bus through which they communicate with each other via their respective input and output buffer circuits coupled to the I/O bus.
FIG. 1 illustrates a block diagram of a conventional system 100 in which a Chip A 102 and a Chip B 104 share an external I/O bus. Chip A 102 and Chip B 104 include output buffer circuits 106 and 108, respectively, and input buffer circuits 110 and 112, respectively. The output buffer circuit 106 of Chip A 102 includes a pMOS transistor 114 and an nMOS transistor 116. The pMOS transistor 114 includes a Pull-Up (PU) gate terminal 118, a drain terminal 120, a source terminal 122, and a well terminal 123. The well terminal 123 is coupled to the source terminal 122, which is in turn coupled to receive a voltage VDD. The nMOS transistor 116 includes a Pull-Down (PD) gate terminal 124, a drain terminal 126, and a source terminal 128. The drain terminal 126 of the nMOS transistor 116 is coupled to the drain terminal 120 of the pMOS transistor 114. The input buffer circuit 110 of Chip A 102 includes a pMOS transistor 130 and an nMOS transistor 132. The pMOS transistor 130 includes a gate terminal 134, a drain terminal 136, a source terminal 138, and a well terminal 139. The well terminal 139 is coupled to the source terminal 138 which is coupled to receive the voltage VDD. The nMOS transistor 132 includes a gate terminal 140, a drain terminal 142, and a source terminal 148. The drain terminal 142 of the nMOS transistor 132 is coupled to the drain terminal 136 of the pMOS transistor 130.
The output buffer circuit 108 of Chip B 104 includes a pMOS transistor 150 and an nMOS transistor 152. The pMOS transistor includes a PU gate terminal 154, a drain terminal 156, a source terminal 158, and a well terminal 159. The well terminal 159 is coupled to the source terminal 158 which is coupled to receive the voltage VDD. The nMOS transistor 152 includes a PD gate terminal 160, a drain terminal 162, and a source terminal 164 coupled to the drain terminal 156 of the pMOS transistor 150. The input buffer circuit 112 of Chip B 104 includes a pMOS transistor 166 and an nMOS transistor 168. The pMOS transistor 166 includes a gate terminal 170, a drain terminal 172, a source terminal 174, and a well terminal 175. The well terminal 175 is coupled to the source terminal 174 which is in turn coupled to receive the voltage VDD. The nMOS transistor 168 includes a gate terminal 176, a drain terminal 178, and a source terminal 180. The drain terminal 178 of the nMOS transistor 168 is coupled to the drain terminal 172 of the pMOS transistor 166.
An external I/O bus 182 couples Chip A 102 with Chip B 104. Referring to Chip A 102, the external I/O bus 182 is coupled to the drain terminal 120 of pMOS transistor 114, the drain terminal 126 of nMOS transistor 116, the gate terminal 134 of pMOS transistor 130, and the gate terminal 140 of nMOS transistor 132. Referring to Chip B 104, the external I/O bus 182 is coupled to the drain terminal 156 of pMOS transistor 150, the drain terminal 162 of nMOS transistor 152, the gate terminal 170 of pMOS transistor 166, and the gate terminal 176 of nMOS transistor 168. By coupling the external I/O bus 182 between Chip A 102 and Chip B 104, a data signal from Chip A 102 may be sent to Chip B 104. More particularly, the output buffer circuit 106 of Chip A 102 sends a data signal through the I/O bus 182 to the input buffer circuit 112 of Chip B 104. Similarly, a data signal can be sent from Chip B 104 to Chip A 102.